Sample-and-hold circuits are commonly used in the front end of analog-to-digital converters (ADCs). A sample-and-hold circuit holds a sample of the continuously changing analog signal for a period of time so that the following ADC circuit can convert the signal to a digital signal representative thereof. For direct-sampling wireless communication systems, sample-and-hold circuits are especially important. They hold samples of the rapidly changing radio frequency (RF) signal for a sufficient time for the relatively slower ADC to process and convert the samples into digital signals representative thereof. As those skilled in the art will appreciate, such digital signals offer some advantages in the processing thereof. In many instances, it is necessary to convert RF signals into digital form because of the inherently more flexible, versatile, and programmable nature of digital signal processing.
Typically, the direct-sampling analog-to-digital conversion of RF signals requires the use of wide bandwidth sample-and-hold circuits, in order to track the rapidly changing RF input signal during the track (sample) mode.
Although contemporary analog-to-digital converters have proven generally suitable for applications such as the direct conversion of RF communication signals to digital signals, such contemporary analog-to-digital converters suffer from power and linearity trade-offs, as well as bandwidth limitations due to their limited tracking ability for multi-GHz signals.
As a result, there is a need for a wide bandwidth analog-to-digital converter having an improved sample-and-hold circuit wherein the linearity and resolution are sufficient to facilitate the construction of communication systems having reduced complexity, reduced cost, enhanced receiver sensitivity, and improved signal quality.